Chuan Seng Tan

Chuan Seng Tan (FIEEE, FIMAPS) received his B.Eng. degree in electrical engineering from University of Malaya, Malaysia, in 1999. Subsequently, he completed his M.Eng. degree in advanced materials from the National University of Singapore under the Singapore-MIT Alliance (SMA) program in 2001. He then joined the Institute of Microelectronics, Singapore, as a research engineer where he worked on process integration of strained-Si/relaxed-SiGe heterostructure devices. In the fall of 2001, he began his doctoral work at the Massachusetts Institute of Technology, Cambridge, USA, and was awarded a Ph.D. degree in electrical engineering in 2006. He was the recipient of the Applied Materials Graduate Fellowship for 2003-2005. In 2003, he spent his summer interning at Intel Corporation, Oregon.

He joined NTU in 2006 as a Lee Kuan Yew Postdoctoral Fellow and since July 2008, he was a holder of the inaugural Nanyang Assistant Professorship. In March 2014, he was promoted to the rank of Associate Professor (with tenure). In September 2019, he was promoted to the rank of Full Professor. His research interests are semiconductor process technology and device physics. Currently he is working on process technology of three-dimensional integrated circuits (3-D ICs), as well as engineered substrate (Si/Ge/Sn) for group-IV photonics. He has numerous publications (journal and conference) and IPs on 3-D technology and engineered substrates. Nine of his inventions have since been licensed to a spin-off company. He co-edited/co-authored five books on 3D packaging technology.

He is a Fellow of IEEE (Class of 2022, citation: for contributions to wafer bonding technology for 3D packaging and integration) and a recipient of the Exceptional Technical Achievement Award from the IEEE Electronics Packaging Society (EPS) in 2019. Since June 2019, he has been a Distinguished Lecturer with IEEE-EPS. He is a Fellow of the International Microelectronics Assembly and Packaging Society (IMAPS) since 2019 and a recipient of the William D. Ashman - John A. Wagnon Technical Achievement Award in 2020.

He was the Chair of the Interconnections Sub-Committee for ECTC’2021. He was the General Chair of the 2020 IEEE Electronics Packaging Technology Conference (EPTC). He is currently an Associate Editor of IEEE Transactions on Components, Packaging and Manufacturing Technology, and received the Best AE Award in 2021. He is a member of the Technical Working Group of the Heterogeneous Integration Roadmap (HIR) on wafer-level packaging. He serves as an elected Member-at-Large to the IEEE EPS Board of Governors from 2022-2024.

Research Interests

• 3D packaging and integration, Group-IV hetero-epitaxy (Si, Ge, Sn) and devices

Current Grants

• Artificial Low-Dimensional Germanium Nanolaser Enabled by On-Demand Quantum Strain Engineering
• CMOS-Compatible Resonant-Cavity-Enhanced GeSn Single-Photon Avalanche Photodiode – Material, Design and Device
• Development of Wafer Scale Abrupt Semiconductor Hetero-junctions with Defect-free Interfaces for Next Generation Electronic and Photonic Applications
• Germanium-Based Materials For Silicon-Compatible Near-IR And Mid-IR Light Source
• Hybrid Ion-Traps for Quantum Computing: Embedded-Glass Ion-Trap on Si Interposer for Large Scale Integration (HIT)
• Nanosystems at the Edge
• Novel Tensile Strained GeSn-on-Insulator Platform and High-Performance GeSn Photodetectors for Mid-Infrared Detection
• Study of Copper Wire Bond Reliability Under Biased Humidity Stress Tests