Edward Hepler

Dr. Hepler earned a PhD in Electrical Engineering from Drexel University, specializing in Digital Systems and Simulation. His thesis topic was: "A Functional Simulation System for MSI and VLSI Systems".

Ed begain his professional career as a Member of Technical Staff in the Processor Design laboratory of Bell Laboratories (at the Indian Hill facility in Naperville, IL) where he helped design high reliability processors used for electronic switching systems. He participated in the I/O architecture of the 3B-20 Duplex processor and the system architecture of the 3B-5 and 3B-2 computer systems. He gained important experience in system design and hardware/software interaction during this time, and wrote the first C compiler for the Motorola MC68000 by porting Bell Labs' portable C compiler (PCC) to that platform.

From Bell Labs, he moved to the Space Systems Division of General Electric (at Valley Forge, PA) where he participated in various hardware and software projects. He ported the GNU C compiler for GE's RPM-40 (a MIPS variant) processor and created a cycle correct simulator and a back-end code re-organizer for it.

Later he joined Commodore Business Machines where he developed chips for next generation Amiga machines. He created the standard cell library used by Commodore for their "AAA" project using procedural layout techniques. He also started the "Hombre" project and generated an implementation of the HP PA-RISC processor for use as the embedded processor in that system.

Ed joined InterDigital Communications (first as a consultant, then transitioned to an employee) where he held the position of Fellow (technical equivalent of Vice President), Embedded Systems Architecture. In this capacity, he provided the implementation architecture for 3G and 4G cellular modems (including InterDigital's SlimChip product). He also led a team that explored the use of "reconfigurable" computer architecture to implement a multi-mode (2G, 3G/R4, 3G/R7, LTE) modem. The team looked at all aspects of the modem across layers 1, 2, and 3, providing cross layer optimizations (including hardware support for the protocol stack).